1. Field of the Invention
The present invention relates to a nonvolatile semiconductor storage device, particularly to a nonvolatile semiconductor storage device that can electrically be rewritable using a variable resistive element.
2. Description of the Related Art
Recently a resistance change memory receives attention as a successor candidate of a flash memory. At this point, it is assumed that the resistance change memory device includes a Phase Change RAM (PCRAM) in which pieces of information on resistance values of a crystalline state (conductor) and an amorphous state (insulator) are stored in a recording layer made of chalcogenide in addition to a narrow-defined Resistive RAM (ReRAM) in which a resistance value state of a recording layer made of transition metal oxide is stored in a nonvolatile manner.
It is well known that a variable resistive element of the resistance change memory has two kinds of operation modes. First, the operation mode is called a bipolar type in which a high resistance state and a low resistance state are set by switching polarities of an applied voltage. Second, the operation mode is called a unipolar type in which the high resistance state and the low resistance state can be set without switching the polarities of the applied voltage by controlling a voltage value and a voltage applied time.
Preferably the unipolar type is used in order to implement a high-density memory cell array. This is because, for the unipolar type, the cell array can be formed without use of a transistor by forming a cross-point type memory cell in which a variable resistive element and a rectifying element such as a diode overlap each other in an intersecting portion of a bit line and a word line. Further, a large capacity can be realized without increasing a cell array area by three-dimensionally stacking and arraying the memory cell arrays (for example, see JP2005-522045 and M. Johnson, et al., 512-Mb PROM With a Three-Dimensional Array of Diode/Antifuse Memory Cells, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38 No. 11, NOVEMBER 2003, p. 1920).
JP2005-522045 discloses a phase change memory device having a three-dimensional memory cell array structure in which the memory cell arrays are stacked on a semiconductor substrate. In the phase change memory device, the bit line connected to the selected memory cell is controlled from an “H” level to an “L” level, and the word line connected to the selected memory cell is controlled from the “L” level to the “H” level, thereby passing a current through the selected memory cell. Binary data is written and read by detecting the current.
However, most non-selected memory cells on the memory cell array are connected to word lines and bit lines that are different from the word line and bit line connected to the selected memory cell, and a bias voltage opposite the selected memory cell is applied to the non-selected memory cells. As a result, a leakage current is generated in the non-selected memory cells to increase a consumption current.
Because the number of memory cells that can simultaneously be selected is restricted from a relationship with the leakage current, it is necessary to perform sequential access every several bytes in the chip in order to perform page access every several kilobytes similar to that of the flash memory, which causes a problem in that a processing speed is lowered.